The present invention relates to the field of electronic circuits, and in particular, programmable phase shift circuitry.
Many electronic systems use a master clock signal to synchronize the operation of all the circuitry and integrated circuit. A fundamental concept in electronic design, synchronous operation is important to ensure that logic operations are being performed correctly. In a system, an integrated circuit may generate its own internal clock based on the master clock signal. For example, this integrated circuit may be a microprocessor, ASIC, PLD, FPGA, or memory. The internal clock is synchronized with the master clock. And in order to ensure proper operation, it is often important to reduce skew for the internal clock of the integrated circuit.
The integrated circuit may use an on-chip clock synchronization circuit such as a phase locked loop (PLL) or delay locked loop (DLL). The synchronization circuit locks or maintains a specific phase relationship between the master clock and the internal clock. When the system is started, it is desirable that the internal clock be locked to the master clock as rapidly as possible. Under some circumstances, such as when there is a wide frequency difference between the two clock, the locking time may be slow. This is because the locking time may be dependent on the slower of the two frequencies. A slower locking time is undesirable because it will take longer for the system to initialize before normal operation. Also, as the master clock varies, it will take longer for the clock synchronization circuit to track these variations.
Therefore, techniques and circuitry are needed to address this problem of clock synchronization circuitry with slow lock acquisition times. Further, it is desirable to provide programmable phase shift selection.
The invention provides a programmable phase shift feature for a phase locked loop (PLL) or delay locked loop (DLL) circuit. The phase shift may be adjusted with equal steps. Each step may be a fixed percentage of the clock period, and will be independent of supply voltage, temperature, and process parameters. Having an on-chip PLL or DLL is an important feature in programmable logic devices (PLDs). Users can use a PLL to improve circuit performance and generate clocks with different frequencies. The phase requirement for the output clock varies depending on the application. A very useful feature for users is the ability to tune the phase of the output clock, and for the result to be independent of process, temperature, and power supply.
In an embodiment, a voltage controlled oscillator (VCO) is implemented using a ring oscillator with approximately equal delay for each stage. Other circuit implementations for a VCO may also be used, including those well known to one of skill in the art. The delay is controlled by the voltage from charge pump The number of stages in the VCO is programmable. This programmability allows a wider frequency range for the VCO. As a higher frequency as specified, a fewer number of stages are needed.
In a specific embodiment, the outputs of the VCO stages are mixed together with a multiplexer MUX1. MUX1 is a programmable multiplexer controlled by configuration RAMs or other programmable elements. The output of MUX1 is fed back to the phase detector through a frequency divider. The output clock of the PLL is connected to stage A of the VCO. If the feedback is not mixed from stage A, the output clock will have a phase shift compared with the input clock, since the feedback must be in phase with the input clock. The amount of the phase shift is determined by the number of stages between A and the feedback.
For example, in the case where there are nine stages in the VCO, and the delay of each stage is xcex94t, then, half of output clock period will equal to nine xcex94t. If the feedback is connected with stage C, then the feedback is two xcex94t behind the output clock. Therefore the output clock is ahead of the input clock by {fraction (1/9)} of the period (9 xcex94t=xc2xd period, 2 xcex94t={fraction (1/9)} period).
By programming MUX1, a user can adjust the phase difference between the output clock and the input clock. This phase difference will be a fixed percentage of the output clock period, and will be independent of process, temperature, and power supply.
In another aspect of the invention, the invention is a phase frequency detector circuit to compare two clock signals and generate a number of outputs to indicate the phase difference between the two clock signals. This circuitry may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. In a PLL or DLL implementation, one of the clocks would be the reference clock or REFCLK, which the user supplies. The other clock is an internally generated clock or CLK that is fed back to the phase frequency detector circuit. In an embodiment, the phase frequency detector circuit has greater than three states. By having a greater numbers of states, the phase frequency detector will be able to generate a more rapidly. The DLL or PLL will have a faster lock acquisition time, even when there is a wide frequency range between the two clock signals. This phase frequency detector may be implemented with the programmable phase shift feature of the invention.
In an embodiment, a circuit of the invention includes a phase detector circuit receiving a reference clock signal; a charge pump connected to the phase detector circuit, and a voltage controlled oscillator connected to the charge pump. The voltage controlled oscillator generates a number of voltage controlled oscillator outputs. Further, the circuit includes a first multiplexer connected to the voltage controlled oscillator, where the first multiplexer selects one of the voltage controlled oscillator outputs as a first clock output. This first clock output may feed back to the phase detector circuit. In an alternative embodiment, the first clock output may used as a clock signal and routed to other circuitry.